1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device with air gaps and a method for fabricating the semiconductor device.
2. Description of the Related Art
Generally, a semiconductor device includes a plurality of first conductive layer patterns and a plurality of second conductive layer patterns. Each second conductive layer pattern is formed between the first conductive layer patterns, but an insulation is between the first conductive layer pattern and the second conductive layer pattern. The first conductive layer patterns may include a gate electrode, bit lines, and metal lines. The second conductive layer patterns may include contact plugs, storage node contact plugs, bit line contact plugs, and vias.
As semiconductor devices are highly integrated, the distance between the first conductive layer pattern and the second conductive layer pattern becomes shorter. The narrower space between the first conductive layer pattern and the second conductive layer pattern may raise a parasitic capacitance between the first conductive layer pattern and the second conductive layer pattern. In particular, a Dynamic Random Access Memory (DRAM) device including bit lines laid adjacent to storage node contact plugs may have a slow operation speed and a deteriorated refresh characteristic because of the increase in the parasitic capacitance between the bit line and the storage node contact plug.
To reduce the parasitic capacitance, the confrontation area between the first conductive layer pattern and the second conductive layer pattern may be minimized, or it may be required to keep a distance between the conductive layer patterns. However, there is limitation in increasing the distance between the conductive layer patterns because the size of semiconductor device products is decreased. Also, one of the ways suggested for reducing the confrontation area is to decrease the heights of the first conductive layer patterns or the second conductive layer patterns. However, the lowering height is necessarily accompanied with the increased resistance of conductive layer patterns.
Therefore, one of the best ways to reduce the parasitic resistance is to decrease the dielectric constant of the insulation layer. Generally, a silicon oxide layer and a silicon nitride layer are used as insulation layers for semiconductor devices. The dielectric constant (k) of the silicon oxide layer is approximately 4, and the dielectric constant (k) of the silicon nitride layer is approximately 7.
Since the silicon oxide layer and the silicon nitride layer still have high dielectric constants, there may be limitation in decreasing the parasitic capacitance. Recently, some layers having relatively low dielectric constants, such as silicon boron nitride (SiBN) and silicon carbon nitride (SiCN), are under development, but their dielectric constants approach approximately 6, which may be not sufficiently low.